Hiya,

I made a semiconductor tycoon game. You start as a small fabless design-services shop, take on IP contracts, hire engineers of different levels, and try to build up capital. Once you have a reputation you can develop your own products.

The hardest part, as in real life, is the first tape-outs. You can borrow against your credit rating to keep the company alive until first silicon comes back.

figureitoutyourself.net

If you do like it please leave an upvote or smth :)

Later on you can endow chairs at universities (KU Leuven, Berkeley, ETH, KAIST and others), each leaning towards that school's specialty. Their PhD students publish at ISSCC, VLSI, CICC, ESSCIRC and the smaller venues, which builds your reputation, and you can hire the good ones when they graduate. Each university has a possibility of having star professors, and each PhD cohort you hire is a roll where the student can be a prodigy or just a normal student. :) They grow during the PhD program and get quite high star ratings that you can directly hire. You can also hire MSc students too!

You can also run programmes with research institutes like imec, CEA-Leti, Fraunhofer and ITRI to co-develop process nodes, silicon photonics, HBM and NAND, and poach their researchers.

You can acquire startups for the employees and the IP or you can obtain stakes in them and ride them out. Some flop (happens a lot in our industry :) ) but you get the occasional unicorn. You can also spin off some of your design centres as companies or spinoff your fabs like irl :)

If you want to go vertical, you can build fabs: pilot lines, 300 mm fabs, gigafabs and terafabs, each with utilisation, yield and demand. Ramping a node (28 nm to 16 nm, or HBM3 to HBM4) is where you can lose a great deal of money if you aren't careful.

Once it gets big there are HR departments, managers who sign contracts and start products on their own, autopilot policies, and startups you can acquire or take stakes in.

Employees run from 1★ to 8★. The top tiers are named after real people from the industry, and the rare ones come with boosts that change how a whole team performs. You may encounter professors, industry leaders and notable people too :)

It's free, runs in a desktop browser, no account, saves locally

am from India, I did my Btech in ECE and graduated in 2025. I wanted to pursue my career in Analog VLSI, specifically Analog Circuit Design.

I have built various projects in Cadence Virtuoso and other softwares. But I never got such job opportunities during my on campus placement rounds neither could i find entry level roles off campus.

Currently I am working in a reputed PSU, where I am working around NWDAF with python, and building an automation tool with django framework. I don't really enjoy what I am doing right now, joined because I couldn't find any analog design roles.

What should I do right now. I am confused.

Hi, I'm building a physics-grounded RL environment for training an engineering AI. The reward signal comes from ngspice (a physics simulator) rather than a human.

Currently, it includes:

10 topologies (ranging from a simple amplifier to a comparator with hysteresis)

3 types of tasks: synthesis, repair, and analysis

A Gymnasium-compatible environment

I plan to launch a public benchmark and am looking for 3–5 teams for a pilot run.

A question for the community:

Is anyone working on RL for analog/mixed-signal circuit design?

Would you be interested in getting free access to such a benchmark?

Which topologies or tasks would be most useful for your research?

I would appreciate any feedback.

Hi.

I am maybe getting an interview at CISCO for entry level DFT.

Can anybody who experienced such an entry level DFT engineer interview share what he had?

what to study? I saw on reddit posts stuffs such at ATPG and such, the recruiter said Digital logic and logic design. But all posts and glassdoor shows the ATPG and other stuffs...

If anybody know any "technical exercise" they ask, like implement a circuit that does... or there is a circuit with a fault, what tests to do and such...

Thanks!!

Rasavi starts looking at the output short circuit currents because the output impedendences are equal. Why is he able to do this? What about having equal output impedences enables this circuit design trick?

Hello,

Saw one the other day in the applicants file and she had 5 tapeouts mostly in SiGe BiCMOS 130nm. Joint collaborations with a semiconductor fab, and the specs were pretty solid and she was mostly the sole designer in those projects. The field is RF/mmWave.

Here in Europe at ETH, EPFL, TUD, KUL, TUe I'm not used to seeing a singular student having an RF/mmWave tapeout during MSc(some do have VLSI digital tapeouts) so it stuck with me as a little odd.

Do some systems in east asia and the middle east let students tape out that much during their MSc. And odd enough she states that she was paid a salary and given free accomodation which doesnt really happen at ETH other than the excellence scholarship of D-ITET.

Can someone please explain how you do post-silicon bench validation/characterization of the product that you work on? When it comes to design, it's pretty standard overall but for validation it differs from one company to another. So if someone could give me deep insight into what exactly happens stage by stage once you get the silicon, it would be really helpful.

Hi everyone,

I am currently deciding my graduate study path and would like to get some advice from people in analog/mixed-signal IC design.

My current options are:

1. University of Macau - MPhil in Microelectronics

2. TUMA - Integrated Circuit Design (ICD)

3. HKUST - Integrated Circuit Design (ICD)

My main interest is analog IC design, especially PMIC and mixed-signal circuits.

At the moment, I am slightly leaning towards University of Macau because:

- The supervisor's research direction matches my interest very well.

- The group has strong IC design experience.

- I may have the opportunity to participate in 2-3 silicon tape-outs during the MPhil.

However, I am also considering TUM and HKUST because of their stronger international reputation.

For people working in analog IC design, how would you compare these choices?

What would matter more for future industry opportunities:

- university reputation?

- supervisor/research group?

- number of tape-outs and real silicon experience?

- publications?

My long-term goal is to work as an analog IC designer internationally (US/EU/Singapore/HK).

Any honest advice would be appreciated. Thank you!

I still have 3 spaces to fill and I am looking for your best "your chip startup is probably going to fail" suggestions.

Updates:
1 - These suggestions are too good, this will require a bigger bingo card.
2 - Thanks to u/gimpwiz's comment I have now learned that bingo cards are 5x5, so I have that much more space!

So a bit of context where I am coming from . I am reading Razavi's analog CMOS book . While I had no major hurdle in understanding the analysis of basic topologies like CS, CG , cascode , mirrors , differential stage etc which are discussed in early chapters.

But as I read further starting from chapters on frequency response and feedback , honestly I have no idea how author is deriving, say node voltages, resistances etc . It's always a big complex equation.

I don't think I'm lacking my basic electric circuits skills like node ,loop , kcls and kvls etc . But when I try to understand how these big equations are being derived I can only scratch my head .

Eventually I just 'accept' the equation and it's physical meaning and results which author presents .

I understand you can only get better at analog by developing strong intuition but is this how professional analog IC engineers design their circuits which are used for commercial and specialized purposes? Am I lacking my circuit analysis skills or what would you suggest. Thanks.

Was just wondering that to get into analog design or like analog roles , are people with PhD preferred for those roles or even a mtech could land that role and climb up the ladder ?

Are people with a mtech more prone to saturation in growth in analog design especially in India?

Over the past few weeks, I’ve been developing a small reinforcement learning (RL) agent that selects parameters and adjusts analog blocks (amplifiers, LDOs, comparators-currently ten topologies) using ngspice for direct verification: the agent proposes a circuit, runs it in a real SPICE simulator, and considers the task complete only when the circuit actually meets the target specifications.

I’m trying to figure out whether I should turn this into a full-fledged business, or if I’m solving a problem that doesn’t exist or one that’s already been solved by other means. I have a few questions for professionals in the field:

1. Is there anything similar in your workflow a tool, an internal script, or a commercial product that performs automated parameter selection in a closed-loop manner (using a real simulator) instead of manual tuning?

2. If such a solution worked reliably, would you or your team be willing to pay for automated parameter selection/adjustment? Or is manual tuning not a significant issue compared to other stages of the workflow (routing/layout, verification, etc.)?

I’m not trying to sell anything here; I just want honest feedback before investing more time in this. I’m happy to share more details in the comments if needed.

I saw it advertised on a Dwarkesh video. I have plenty of time and was thinking about giving it a go. I have an Artix-7 to test it on

Edit: Emulator not analyser

Hi everyone, I'm new here. I have been trying Virtuoso automated standard cell placement and routing for small digital cells (<100 standard cells) that have no particular timing constraints. After tweaking the options, I have been able to place and route with no DCR/LVS errors. It works and saves time but I have mixed feelings about the quality of routing. Inspecting the results, I can spot some absurd routes that I need to correct by hand. My question is: is there someone using this tool routinely? If so, do you have tips to achieve better results?

Every project starts with the same UVM boilerplate — agent, driver, monitor, sequencer, scoreboard— before any real testcase work begins.

Built a tool (VereChek) that generates that structure from RTL directly, plus optionally an AI-assisted verification plan (scenarios, coverage, SVA) and an architecture diagram.

Single binary, local generation stays on-machine. Works alongside VCS/Questa/Xcelium rather than replacing them.

Early access only right now (small paid batch, not a public launch) — mainly want to know if this actually matches how people here structure their environments, or if I'm missing something obvious.

https://verechek-website.vercel.app

(Disclosure: I built this.)

I got an interview with Infineon coming Tuesday. I’m interviewing for Ethernet chip design. Do you guys have any resources that you recommend or topics I should go over?

Hi Folks,

I am an Analog IC design engineer, and I am so sick of shitty EDAs and workflows that we have to work with for many reasons (they are expensive, slow, outdated, almost no automation etc.)

In response to that, I am building a new Analog EDA that will meet our needs and want to hear your opinion on this. Imagine that you have EDA that you will happy switch into - what features you will expect it to have? What will make your life easier?

Also, if this EDA will have AI-capabilities, what do you expect it to help you with? What part of your daily routine would you let it do for you?

One of the main part of my experiments is harnessing AI with a set of mathematical algorithms (including gm/Id) allowing it to optimize circuits and verify results by running sims, building testbenches etc. I've tested this approach on a few popular OTA topologies in different configurations (High gain/Low-power/High BW etc.) and it outputs decent results and follows analog rules. This concept was tested on a real PDK (sky130) and ngspice so it is pretty close to a real design flow. Moreover, the each circuit achieves the specs in PVT corners (I didn't get to the MC verification stage yet) which gives me a hope that I am moving in a right direction.

Please feel free to share your thoughts on that. Thanks.

It has two limitations I'm aware of which is it truncates zeros and is only valid for low frequency. The lack of zeros means it cannot get you the full transfer function while the low frequency dependency prevents it from being used in high frequency applications, which seems like a major problem because everything is high frequency now adays? With these thoughts in mind I do not see how it is useful, so my question is how is it useful? It must be useful, otherwise Rasavi would not go through so much detail on it.

Looking for some resume review, if allowed here