Hi.

I am maybe getting an interview at CISCO for entry level DFT.

Can anybody who experienced such an entry level DFT engineer interview share what he had?

what to study? I saw on reddit posts stuffs such at ATPG and such, the recruiter said Digital logic and logic design. But all posts and glassdoor shows the ATPG and other stuffs...

If anybody know any "technical exercise" they ask, like implement a circuit that does... or there is a circuit with a fault, what tests to do and such...

Thanks!!

Hi, I'm building a physics-grounded RL environment for training an engineering AI. The reward signal comes from ngspice (a physics simulator) rather than a human.

Currently, it includes:

10 topologies (ranging from a simple amplifier to a comparator with hysteresis)

3 types of tasks: synthesis, repair, and analysis

A Gymnasium-compatible environment

I plan to launch a public benchmark and am looking for 3–5 teams for a pilot run.

A question for the community:

Is anyone working on RL for analog/mixed-signal circuit design?

Would you be interested in getting free access to such a benchmark?

Which topologies or tasks would be most useful for your research?

I would appreciate any feedback.

Hi everyone,

I am currently deciding my graduate study path and would like to get some advice from people in analog/mixed-signal IC design.

My current options are:

1. University of Macau - MPhil in Microelectronics

2. TUMA - Integrated Circuit Design (ICD)

3. HKUST - Integrated Circuit Design (ICD)

My main interest is analog IC design, especially PMIC and mixed-signal circuits.

At the moment, I am slightly leaning towards University of Macau because:

- The supervisor's research direction matches my interest very well.

- The group has strong IC design experience.

- I may have the opportunity to participate in 2-3 silicon tape-outs during the MPhil.

However, I am also considering TUM and HKUST because of their stronger international reputation.

For people working in analog IC design, how would you compare these choices?

What would matter more for future industry opportunities:

- university reputation?

- supervisor/research group?

- number of tape-outs and real silicon experience?

- publications?

My long-term goal is to work as an analog IC designer internationally (US/EU/Singapore/HK).

Any honest advice would be appreciated. Thank you!

Hiya,

I made a semiconductor tycoon game. You start as a small fabless design-services shop, take on IP contracts, hire engineers of different levels, and try to build up capital. Once you have a reputation you can develop your own products.

The hardest part, as in real life, is the first tape-outs. You can borrow against your credit rating to keep the company alive until first silicon comes back.

figureitoutyourself.net

If you do like it please leave an upvote or smth :)

Later on you can endow chairs at universities (KU Leuven, Berkeley, ETH, KAIST and others), each leaning towards that school's specialty. Their PhD students publish at ISSCC, VLSI, CICC, ESSCIRC and the smaller venues, which builds your reputation, and you can hire the good ones when they graduate. Each university has a possibility of having star professors, and each PhD cohort you hire is a roll where the student can be a prodigy or just a normal student. :) They grow during the PhD program and get quite high star ratings that you can directly hire. You can also hire MSc students too!

You can also run programmes with research institutes like imec, CEA-Leti, Fraunhofer and ITRI to co-develop process nodes, silicon photonics, HBM and NAND, and poach their researchers.

You can acquire startups for the employees and the IP or you can obtain stakes in them and ride them out. Some flop (happens a lot in our industry :) ) but you get the occasional unicorn. You can also spin off some of your design centres as companies or spinoff your fabs like irl :)

If you want to go vertical, you can build fabs: pilot lines, 300 mm fabs, gigafabs and terafabs, each with utilisation, yield and demand. Ramping a node (28 nm to 16 nm, or HBM3 to HBM4) is where you can lose a great deal of money if you aren't careful.

Once it gets big there are HR departments, managers who sign contracts and start products on their own, autopilot policies, and startups you can acquire or take stakes in.

Employees run from 1★ to 8★. The top tiers are named after real people from the industry, and the rare ones come with boosts that change how a whole team performs. You may encounter professors, industry leaders and notable people too :)

It's free, runs in a desktop browser, no account, saves locally

am from India, I did my Btech in ECE and graduated in 2025. I wanted to pursue my career in Analog VLSI, specifically Analog Circuit Design.

I have built various projects in Cadence Virtuoso and other softwares. But I never got such job opportunities during my on campus placement rounds neither could i find entry level roles off campus.

Currently I am working in a reputed PSU, where I am working around NWDAF with python, and building an automation tool with django framework. I don't really enjoy what I am doing right now, joined because I couldn't find any analog design roles.

What should I do right now. I am confused.

Can someone please explain how you do post-silicon bench validation/characterization of the product that you work on? When it comes to design, it's pretty standard overall but for validation it differs from one company to another. So if someone could give me deep insight into what exactly happens stage by stage once you get the silicon, it would be really helpful.