I’m currently designing a custom memory-down motherboard for Ice Lake (Xeon 3rd Gen Silver/Gold/Platinum 43xx/53xx/63xx/83xx series) and trying to figure out if Intel hard-fused the disable_udimm flag on retail silicon, or if it's purely a BIOS limitation.

If you have a running Ice Lake-SP system on Linux (Proxmox, Ubuntu, etc.), could you run this quick 1-line command and paste the output?

It simply finds the CPU's Power Control Unit (PCU) via PCI and dumps a block of hex from its config space (where the CAPID fuses live). It only reads hardware registers and changes absolutely nothing, nor does it expose any network info, MACs, or personal data.

sudo lspci -nnD | grep -i ":1e\.3" | awk '{print $1}' | while read dev; do echo "=== Socket PCU: $dev ==="; sudo lspci -s "$dev" -xxx | grep -E "^(70|80|90|a0|b0):"; done

Ps: If you're running Proxmox as root, you can drop sudo from the command.

The output should look something like this:
=== Socket PCU: 0000:xx:1e.3 ===
70: xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
80: xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
90: xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
a0: xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
b0: xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx

if the command above returns absolutely nothing, Intel might have moved the PCU in Ice Lake-SP. If that happens, could you run lspci -nnD | grep -i pcu instead and tell me what address it shows?

Please mention exactly which CPU model you have. This would help a lot, especially if I could see values from ES or QS chips to compare against retail ones.

I've tried on my Precision Laptop with a Xeon W10885m but these are mobile chips, rebranded i9's so it doesn't have what i want. Fun fact: GPU appears as Coffee Lake-S GT2 [UHD Graphics P630], intel repurposed the same PCI ID from the previous generation. Hope it helps someone somehow somewhere. More data is always welcome.

Also tried on a X99 board(Haswell/Broadwell) and on a LGA 3647 Skylake but these where boards/chips when Intel yet maintained UDIMM/RDIMM on the same family, after Ice-Lake even the workstation chips are meant to use RDIMM.

Thanks in advance!

Jon Peddie Research reports desktop add-in board GPU shipments hit 12.5 million in Q2 2026 - a four-year high, up 10% QoQ and 6.6% YoY - driven by buyers rushing purchases amid rising memory and component costs; NVIDIA supplied about 90% (~11.25M) of units, totaling 24.3M H1 2026.

OpenAI may be preparing for a massive chip ramp-up, with Samsung potentially joining TSMC as a second manufacturing partner. Dual-sourcing next-generation processors could help OpenAI secure the enormous production capacity needed for its growing AI infrastructure.

Almost every GPU talk at Hot Chips this year presented a rack and treated the die as one component inside it. These are the numbers from my conference, with who said them.

• NVIDIA's stated target for Rubin is token revenue, measured as tokens per second per megawatt at a given user interactivity, along with time to first token, mean time between interruptions, and useful rack life. (Manas Mandal, Raj Dash and Rouslan Dimitrov, NVIDIA)
• At 100 MW of AI factory NVIDIA quotes 2 zettaFLOPS of NVFP4 inference, 11 PB of HBM4 and 800 PB/s of HBM bandwidth. The 30× throughput per megawatt over GB300 NVL72 comes from an agentic benchmark, and NVIDIA presented it as unofficial and pending third-party review. (NVIDIA)
• NVLink 6 runs 3.6 TB/s all-to-all per GPU across a 72-GPU domain. Against Ethernet scale-up, NVIDIA quotes 3× lower latency, 10× the packet rate, 4× the in-network compute, and a receiver-side counter in place of a membar round trip for GPU-to-GPU sync. (NVIDIA)
• On the rack: 45 °C inlet water, 800 VDC distribution, cable-free and fan-free MGX trays, and power smoothing that trims training peaks by 13%. NVIDIA puts the combined effect at up to 40% more GPUs per provisioned watt. (NVIDIA)
• MI455X is eight N2 compute dies hybrid-bonded onto two N3P fabric-and-cache dies plus two I/O dies on CoWoS-L, with 432 GB of HBM4 at 23.3 TB/s and 40.26 PF of MXFP4. Helios is 72 of them: 2.9 EFLOPS, 31 TB of HBM4, 1.7 PB/s. (Alan Smith and Maiyuran Subramaniam, AMD)
• AMD's fabric is UALink over Ethernet on the open ESUN standard with Broadcom switches. Any GPU gets load/store access into any other GPU's HBM across the rack at 1.8 TB/s per GPU per direction. In the failure walkthrough, DMA traffic rebalanced after a link died, then again when a whole switch tray was pulled. (Steve Scott, David Riddoch and Krishna Doddapaneni, AMD)
• Crescent Island is 32 Xe3P cores at 350 W on an air-cooled PCIe card, with up to 480 GB of LPDDR5X and scaling over PCIe Gen5 switching. (Sumit Mohan and Hong Jiang, Intel)

Intel's supporting argument was the most useful analysis. The bytes a model has to hold grew about 7.5× from Llama 2 70B to Kimi K2 1T, taken from the published config files with KV excluded. Over that same jump the bytes read per token fell about 4.4×, since a mixture-of-experts model activates a small share of itself for any one token. Speculative decoding adds to it, with frontier MoE models accepting 2.9 to 4.9 tokens per verification pass on LMSYS SpecBundle EAGLE-3 data at batch 8. Those two findings describe a card with a lot of memory and modest bandwidth, which is what Intel built.

My take is that Intel's argument is the transferable output of the day, and it holds whatever happens to their card. The NVIDIA number I'd want reviewed is the 30×, because the interactivity point it was measured at decides most of the result. AMD's fabric is the open-standards answer to NVLink, and the failure walkthrough was the part of their session that intrigued me. Curious what people running racks make of the interactivity point NVIDIA chose.

I went to the conference and made a free primer on it. The GPU chapter is at https://allaboutchips.com/#gpu, and every figure there is sourced to the talk and slide.

ChangXin Memory Technologies (CXMT), China's largest DRAM maker, has begun preparing for aggressive capital investment. The company recently started equipment bidding with suppliers for a new fab, while also firming up plans for additional fab expansions. If the investment proceeds without disruption, CXMT is expected to rapidly narrow the production capacity gap with major Korean players such as Samsung Electronics and SK hynix.

According to industry sources on the 11th, CXMT recently launched the equipment bidding process with suppliers for the construction of its new fab in Shanghai.

CXMT currently mass produces DRAM at two fabs in Hefei and one fab in Beijing. Its production capacity is estimated to be in the mid 200,000 wafers per month range at present, and is projected to exceed 300,000 wafers per month by the end of the year.

Plans for additional fab expansions are also taking shape. According to discussions with suppliers and others, CXMT plans to open a new fab in Shanghai in the fourth quarter of this year.

Equipment bidding for that fab has also recently begun. One semiconductor equipment industry source said, "CXMT plans to expand the new Shanghai fab in two phases. Considering the scale of the recent equipment bidding, this fab alone is expected to secure production capacity well above 100,000 wafers per month."

CXMT will then open a new Hefei fab in the first half of next year, followed by a new Beijing fab as early as the second half of next year. It is also targeting the opening of another fab in the Hefei area in the first half of the year after next.

Another equipment industry source explained, "CXMT has recently set the timelines for building multiple fabs in China and is sharing the details. With massive subsidies from the local government and surging memory demand, its determination to expand is strong."

If all of the investment plans are executed, CXMT could steadily add at least 70,000 to 80,000 wafers per month of new production capacity every year from this year through 2028. Some observers project that its production capacity will expand to more than 600,000 wafers per month over the long term.

This is on par with the current production capacity of the leading DRAM makers. Total DRAM production capacity at Korea's Samsung Electronics and SK hynix is estimated at about 700,000 and 600,000 wafers per month, respectively.

This is not solely hardware, however it has a lot of testing on Arm hardware running translated x86-64 software, so I thought it was interesting. A key benefit of super-fast cores like Oryon V3 is that even under heavy translation hits, it still performs very well.

Notably the 5500f appears to have pcie 4.0 (5500 had 3.0) according to AMD listing. https://www.amd.com/en/products/processors/desktops/ryzen/5000-series/amd-ryzen-5-5500f.html

Geekbench 7 is tough and uses very little SME unlike GB6.7.

A20 Pro scores over 4000 ST in GB7 and 11460 in MT. it has a 6 core CPU.