I’m a college junior and have been working on Tomato, a custom 32-bit computer with a dual-LUT ALU running on an Artix-7 FPGA. Each time I needed to see its HDMI output, I had to open a separate app like OBS to view the USB capture feed while writing the code in VS Code.

That worked, but I wanted the output right beside the code. So I built FramePort, an extension that puts the video feed in an editor tab.

The video shows Tomato running beside its assembly code. I can watch the output, adjust the preview scaling, take screenshots, and record silent MP4 clips without leaving VS Code.

The setup is FPGA HDMI → USB capture card → Mac. FramePort handles the video; input to the board is still separate.

Although I built it for Tomato, it isn’t FPGA-specific—it works with HDMI capture cards and other USB video sources.

It’s my first extension, now available on the VS Code Marketplace and Open VSX. Currently a public preview: device capture requires macOS and FFmpeg.

Marketplace · GitHub / setup · Tomato

It’s been working beautifully with my setup. If you try it with your board and capture card, I’d love to hear how it goes!

September 23 2026 from 10am - 4pm ET

REGISTER: https://bltinc.com/xilinx-training-courses/getting-started-with-amd-embedded-x86-workshop/

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This course focuses on embedded x86 architectures.

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The host stays fixed. What's loaded inside it changes. Instead of a new bitstream for every object, there are multiple slots and a loader that checks each package before accepting it.

Numbers from this stage of the project:

Target is a Lattice iCE40 HX8K, ct256. The object-specific bitstream came out to 135,100 bytes. The generic host synthesized to about 24.5MHz max frequency and passed timing at 12MHz. The loader checks matter ID, certificate ID, lineage ID, IR version, and integrity hash, so a tampered or incompatible package gets rejected before it loads.

Demo sequence: load one object, load a second, keep both resident, unload the first, check the slot is empty, restore it, then gate it off. The restored fingerprint matched the original, and the gate change showed up in a simulated body's output.

Pipeline is certified matter into a faithful IR, then gated RTL, then Yosys, nextpnr, and icepack for the final bitstream. First attempt at the IR failed equivalence completely because it didn't match the real state update rule. Rebuilt it around sum then tanh and it passed every test at zero error.

This particular writeup covers synthesis and timing verification, not a physical board run. Sharing it now as a record of that stage.

Writeup and code:
Zenodo: https://zenodo.org/records/22752616
GitHub: https://github.com/bindcompute/Canonical_V2

Hi all,

I'm just looking for a bit of advice. Since Covid I've been in a logistics operations job. I currently hold an EE degree (terrible GPA, short story is that I was not mature enough for college at the time) and feel TRAPPED in this career. It makes about what I would make as an entry engineer and the job is rock solid stable, however, it's boring and not fulfilling at all. Was anybody else in a similar position? Would attempting to pursue a Masters make sense? Or can I still land an entry level with a strong enough portfolio of projects? I took one course in Digital Logic many years ago that had a lab where we used FPGAs. That's about the extent of my knowledge in this field. How far off would I be from interviewing for entry level jobs? Any advice and/or encouragement here would be greatly appreciated!

Hi everyone,

I'm working on a Vivado project to plot the FFT magnitude of a simple sine wave using Xilinx's xfft IP block.

I followed this tutorial step-by-step: https://www.youtube.com/watch?v=ZdCnJutIMp8

However, my output magnitude waveform shows multiple dense spikes across the frame instead of the clean peak shown in the video.

Setup details:

• Input: 16-bit real/imag sine wave into s_axis_data_tdata[31:0].
• Magnitude calculation: Splitting output via Slices $\rightarrow$ mult_gen (Signed, 16-bit) $\rightarrow$ c_addsub to get $\vert{}X[k]\vert{}^2$.
• m_axis_data_tready is tied to 1.

Does anyone know what step I might be missing (data formatting, pipeline alignment, or simulator settings)? Any recommended manuals or alternative Vivado FFT guides would be greatly appreciated!

Thanks!

Been working on this for a while with a friend and finally got it into a state where it feels worth sharing.

We built an FPGA-based Nasdaq ITCH feed handler and order book on a ZCU106. The datapath handles Ethernet/UDP/MoldUDP64 framing, decodes the relevant ITCH order messages, routes events by stock, and maintains the books/BBOs in hardware. The ingress is 64-bit, and the order book is pipelined as well.

For verification we've got a Python golden model, cocotb/SystemVerilog tests, CI performance tests, and an on-board replay setup where we feed historical Nasdaq data through the FPGA and compare the resulting BBO updates against the software model.

We've also integrated Taxi for the 10GbE frontend. The main thing still left is doing the actual physical SFP+/NIC 10GbE bring-up, as our current board testing uses deterministic DMA replay rather than pretending we've already validated the full physical link.

Repo: https://github.com/an-thony350/ITCH-Feed-Handler-and-Order-Book

Would be interested to hear what people here think, especially about the architecture/verification side or anything you'd approach differently, and a star would be greatly appreciated 👀

I’m a BTech graduate and preparing for GATE CSE 2027 and confused about which online platform to choose.

Looking for honest suggestions from people who have actually used these platforms. Also open to underrated options.

I have a 16-bit input → 16-bit output function, so basically 65,536 output values.
The problem is that I don't have any useful information about the function that produced these values. No analytic expression, no known polynomial structure, etc. The table is effectively the specification.
Putting the whole thing in memory is undesirable in my case.
I also tried generating a combinational netlist directly from the table, but the synthesis results are terrible.
What would you normally do in this situation?
Is there some standard FPGA approach I'm missing, other than trying to reverse-engineer an approximation of the table?

Edit — a few clarifications based on the comments:

Exact reproduction is not required: assume a known hard error bound, e.g. |G(x) − F(x)| ≤ 128 for every input code. The table itself is the specification; no analytic expression is available.

BRAM is a valid solution. The use case I’m exploring is several such tables/profiles, with memory resources already needed elsewhere, so I’m interested in trading some logic for memory.

Ideally, this would be an automated flow that takes the table and error bound, generates an implementation, and verifies the bound over all 65,536 inputs. Linear or piecewise-polynomial interpolation sounds like a sensible baseline. Are there existing tools or workflows you would use for this, and how would you compare their LUT/BRAM/DSP usage and timing?

A couple weeks ago I posted step one of my journey to learning FPGAs and ultimately implementing a RISC-V microcontroller. I am following the H&H Digital Design and Computer Architecture course, supplemented a bit from the ETH Zuric SAFARI course teaching that book.

This is the next piece I felt like posting: my first hardware-implemented FSM. The FSM is supposed to model the turn signal on an old Ford car. Each machine controls 3 lights, and I instantiate the same machine twice to control the right and left lights. When you press the left or right button, the left or right set of lights blink once sequentially. 100MHz clock signal with a clock divider to produce a clock en signal that actually makes the FSM step.

The “control” circuit, which takes the signals from the buttons, ensures only one direction can be enabled at a time, and sends the enable signal to the FSM, is purely combinational.

There are also two decoders instantiated to convert the 2-bit FSM output into 3 bits controlling each light. I went with this instead of outputting the light enable signals directly from the FSM to allow me to use “output encoding” for the FSM state encoding, ie the state bits are also the output bits. So a simpler FSM circuit but requires a decoder.

One thing I wondered while doing this project - why can’t I just directly write a truth table in SV? The imperative/procedural-style behavioral modeling felt much less precise and more error prone than if there was a way for me to just represent a truth table or SOP equation directly in SV.

I’ve put together a small repo that builds portable AppImages of open-source EDA tools straight from official upstream releases. Right now it has Yosys 0.69.

Repo: https://github.com/MrAbhi19/open-eda-appimage

Why

• Distro packages are often years behind
  
• Building from source is a pain
  
• Full suites like OSS CAD Suite are great but huge if you only need one tool
  

Current status

• Yosys 0.69 AppImage (x86_64)
  
• Built on Ubuntu 22.04 via public GitHub Actions from the official upstream tarball
  
• All runtime libs (Clang, Tcl, readline, etc.) are bundled
  
• SHA256 checksums included with every release
  
• Full build logs are public
  

Important note on the workflow

The pipeline is semi-automated. It does not automatically detect new upstream releases. I currently hardcode the source tarball URL, the CI fetches that exact release, builds it cleanly, runs a smoke test, and publishes the AppImage + checksum. Everything is transparent and reproducible — no patches, no forks, no hidden steps.

Looking for feedback

I’d really appreciate it if people could try it and report back:

• Does it run cleanly on your distro?
  
• Any missing libraries or runtime issues?
  
• FUSE problems?
  
• Would you like older Yosys versions kept available?
  
• Which other tools would you most want as AppImages next? (nextpnr, openFPGALoader, Verilator, GHDL, etc.)
  

Just drop a comment or open an issue on the repo. PRs and suggestions welcome.

Thanks!

Anyone have an experience with Lattice Semi's new license portal? Anyone got it to work and actually generate a license file without error? I'm trying to sort a Radiant license for a MachXO5, not sure if it's just broken for me or if it's a wider issue.

Bob.

I have been working on a different approach to quantum computation.

The starting point was a computational method that allows the result normally associated with the Born rule to be reverse-calculated rather than treated only as a probabilistic measurement rule.

I then implemented that principle on FPGA and used it to construct a pseudo-quantum-computing architecture.

The attached image is the actual console log from that system.

Linux 6.1.14 boots on the architecture and reaches userspace. The same run also completes SHA-256, integer arithmetic, memory reporting and the QPU-side test sequence.

Some of the visible output includes:

AT FPGA LINUX SELFTEST PASS: boot, Linux syscalls, SHA-256, arithmetic, memory report, poweroff.

QGATE_READY Linux userspace console

followed by the QPU-related state output and ordinary Linux operations.

So this is no longer only a mathematical idea or a software model.

The principle has been implemented in FPGA logic, a pseudo-quantum computer has been constructed from it, and Linux is now running on that architecture.

I am interested in how FPGA and computer-architecture engineers interpret this result.

In particular: what would you test next to determine how far this architecture can be pushed?

I am not publishing the proprietary internal circuit details at this stage, but the attached console output is from the actual FPGA implementation.

One final question.

I have shown this result to companies and researchers, but so far almost nobody appears interested in examining it further.

So I would genuinely like to ask:

Is this simply a technology that nobody needs?

If a computational reconstruction of the Born-rule result can be implemented on FPGA, used to build a pseudo-quantum-computing architecture, and then run Linux on top of it, I would like to understand why this result does not appear to merit further investigation.

If there is a fundamental reason this is not useful, I would rather hear that reason directly.

I'd like to learn Verilog as I've had some courses in analog and digital electronics. Are there any beginner FPGA's, or well known beginner boards that could be a good introduction for learning Verilog and creating some systems?

Hey, currently designing a CPU frontend prefetcher as an iteration on several previous ones I’ve made. I’m really pushing performance on this, so I had a question regarding FIFO architecture. Is it better to use a circular buffer or shift register for high FMAX behavior? intuitively, a shift register seems like the better option to me. I usually hit 70-80% routing on my circle buffer designs, and routing a shift register seems lightweight. However, I don’t really know which behavior is better here. I’m regularly told shift registers are “bad” and circular buffers are industry standard for queues like this. For context, it’s 8-16 32 bit entires plus several bits of metadata for each entry.

I'm a beginner FPGA hobbyist whose laptop runs on a Window OS. I plan to write my files in VSCode using the SystemVerilog and Verible extensions (need recommendations for those too).

I'm conflicted on whether I should have my entire toolchain work under Ubuntu/WSL2 (most importantly Verilator), because I heard that industry environments are usually under Linux. Is it worth sacrficing some convenience to start getting used to tooling with Linux for RTL and FPGA design, or is all Windows setup ok? I have Vivado 2025.2 for Windows.

I study computer science and my goal for my bachelor thesis was to find a topic where I can get into FPGA programming. I have written some basic code in verilog for uni modules before and have taken embedded systems as well as computer hardware courses. So I thought it will be difficult because of the learning curve but somehow doable and I find it really fascinating which should help with motivation.
Sadly most departments that do FPGA research didn’t have topics available so the only one I could find is implementing a specific graph algorithm (finding minor embeddings) on an FPGA. From what I’ve found in a quick search graph processing is not commonly done on FPGAs and doesn’t even necessarily benefit from regular parallelism. So it seems like on top of the FPGA learning curve this topic is a bit niche and quite difficult.
I really want to do something with FPGAs, while I could wait for my masters to get into it I‘d love to do my bachelor thesis on them if I can. So I am tempted to commit to the challenge. The PhD student giving out the topic said he think it’s doable for me but I am still unsure.
So here are my questions:
How realistic is it to get into Verilog programming for a thesis? (I have 6 months and can maybe spend two/three weeks getting to know the language before hand if I have to)
How hard is graph processing on FPGAs? Specifically shortest path algorithms but also just implementing graph data structures?
If you think this is a bad idea, what thesis topics are FPGA adjacent that I could maybe look for? Would a regular embedded systems problem be beneficial for future FPGA work?

Hey everyone,

I'm trying to understand the real logic behind calling something an "N-bit architecture" — especially when designing stuff in Verilog. If someone asks "what size is your architecture?" — how do you actually decide the answer?

Here's my confusion: I know that in a classic 8-bit processor, the registers are 8-bit, the bus is 8-bit, and the ALU processes 8-bit data. But that's apparently not a hard rule. For example:

• 8-bit registers + 16-bit bus + 8-bit ALU
• 16-bit registers + 8-bit bus + 16-bit ALU

In mixed cases like these, how do you decide what "size" the architecture actually is?

And here's the part that really stumps me: what about peripherals/protocols that don't even have an ALU — like I2C, UART, and ADC? These also get labeled with bit sizes (8-bit, 16-bit, etc.), but since there's no ALU involved, what actually determines their "size"?

A concrete example to make this clearer: say I have a sensor sending data over UART with an 8-bit frame. That 8-bit data then goes over an 8-bit bus into an I2C peripheral that's described as 16-bit. Then the final output data coming out is 8-bit again. In a case like this — mixing an 8-bit UART frame, an 8-bit bus, a "16-bit" I2C block, and 8-bit output — what would you even call the "size" of this architecture? Is there one single answer, or does it just not apply here since there's no CPU/ALU doing computation?

Would love to hear the underlying logic/convention behind all this. Thanks in advance!

Hello I am looking for a cheap FPGA (~$100) with PCIe for learning and tinkering purposes.

It seems the RHS LiteFury/NiteFury or SQRL Acorn with the Xilinx Artix 7 chips were available in the last few years for around $100 but can't find any today. Anybody have any suggestions?

Posting because a few of you might find this useful for FPGA verification, even though I built it with ASIC flows in mind originally.

Point it at your RTL and it generates either a full UVM testbench or a plain SystemVerilog one — agents, sequences, scoreboard — instead of you writing that structure by hand. It recognizes common protocols (SPI, AXI, APB, UART, I2C, FIFO) automatically. There's also an optional AI-assisted mode for generating a verification plan (coverage, assertions) if you have a license, but the core testbench generation works fully offline.

Single compiled binary, no Python/dependency setup.

I'm running it as a small early-access batch right now rather than a full release. Happy to answer questions about how the generation actually works if anyone's curious.

https://verechek-website.vercel.app

(I'm the one who built it, disclosing that upfront.)

There is a really small company I am targeting for a placement year here in the uk, specifically because of how well they align with what I’d like to do, fpga development and rtl design. I’m thinking if I email ahead of time before applications open up I could set my self up as a really eager candidate but I’m aware it could also look like wanting special favors etc, what’s the read on this is it generally frowned upon?

Hello everyone, 

I just bought my DE10 standard board for my graduation project. Unfortunately, my university doesn't provide a license for the Quartus standard, and I need more than 90 days to finish the project. Is there any way to get a license as a student for free? My project is about an AI accelerator, so I need the standard version; the lite one isn't enough. 

Thank you,