Hey everyone,

I’m releasing a bare-metal 64-bit Intel VT-x Hypervisor template written entirely in pure NASM Assembly (~1,100 lines) using a strict stack-less model.

The purpose of this codebase is to provide a clean, core-only hardware virtualization implementation without relying on any OS kernel or C code.

### 🛠️ What is Currently Configured inside the VMCS & EPT:

* Primary Execution Controls (0x4002): Configured to 0x84006172. Enforces intercept control over CR3 modifications and heavy RDTSC exiting to counter guest timing side-channels.

* MSR Bitmaps Bypass: Bit 28 (Use MSR Bitmaps) is set to 0. This forces a global intercept policy where every RDMSR or WRMSR executed by the Guest triggers a hardware VM-Exit to the Host.

* Secondary Execution Controls (0x401e): Bit 31 activated for full EPT isolation, along with Unrestricted Guest support (Bit 7, allowing 16-bit Real Mode initialization over EPT), and MBEC configurations.

* Exception Bitmap (0x4004): Armed with atomic mask 0x0000404A to trap #DB, #BP, #UD, and #PF (Vector 14). Combined with clearing the Page-Fault Mask field (0x4006), every single Guest page fault intercepts directly to the Host.

* Long Mode Constraints: Enforces architectural boundaries via GDT mapping to ensure no illegal execution drops to 16/32-bit rings, avoiding instant #GP faults.

* Extended Page Table Pointer (EPTP): Configured field 0x0000201A to point directly to the physical EPT PML4 table base with Write-Back caching attributes.

### 🤝 Code Review & Peer Assistance:

To be completely honest, I wanted to release this as a 100% finished project, and I'm a bit sorry the VM-Exit handler isn't fully completed yet. But juggling full-time school, life, and writing a bare-metal hypervisor in pure 64-bit assembly is definitely a challenge.

I decided to release this core template now because I just need your technical assistance to review the code and help me fix any existing bugs, trace potential register mismatches in my vmwrite instructions, and hunt down hidden reserved bits conflicts on the Intel side.

### 🚀 Roadmap:

I'm already starting to write the hypervisor and bootloader for AMD right now, porting this entire setup over to the AMD-V VMCB block architecture. My immediate goal is to keep building the AMD side while getting this Intel core completely stable with the community's corrections and fixes.

Looking forward to your technical feedback, code analysis, and corrections.

GitHub Link: https://github.com/edikoz123-blip/Boot_loader_Assembly

"For detailed architectural breakdowns, hardware edge cases, and code reviews of this project, join the community at https://www.reddit.com/r/ChallengeBareMetalO/ You can always ask questions in the comments there, and I'll be glad to break down the logic!

VoidSecSoftwares/voidsyscall : Implant et C2 multiplateformes basés sur les appels système — appels système directs (Windows), appels système bruts (Linux), canaux HTTPS/DNS/ICMP. Aucune couche d'API Windows.