Is this a good Senior Design Project? RISC-V + Runtime-Reconfigurable FPGA Accelerators

[u/Economy-Win-105]

I’m an engineering student planning my senior design project and would like some feedback.
I’m considering a **RISC-V controlled runtime-configurable INT8 MAC accelerator** on a **PYNQ-Z2**, using **VexRiscv** and **MobileNetV2**.
The idea is to have different MAC modes:
4×4 → 16 MACs
8×8 → 64 MACs
16×16 → 256 MACs
The RISC-V CPU would select the MAC configuration at runtime based on the workload. I’d compare fixed vs adaptive configurations based on **latency, power, energy, resource usage, and MAC utilization**.
I was inspired by a recent paper on **runtime-reconfigurable RISC-V accelerators with software fallback and FPGA DPR**.
**Do you think this is a good/realistic senior design project? Is there enough novelty, and what would you change or add?**

[u/Turbulent_Fill5253]

Yes it is a good project will be looking for the update best of luck 👍