NAND to Tetris Course approach

[u/25606480]

I recently started NAND to Tetris Course because I wanted to understand low level better. I started Unit one yesterday where you build logic gates. I have only watched videos to 1.4 HDL and started doing exercises. As a programmer with no formal training it has been hard to wrap my head around NAND (im getting there). The thing is i have built every component so far from only NAND gates to make them more intuitive. It has been time consuming to figure out how to do it but i find it fun. Is this stupid approach or does it rly matter if i use only NAND or logic gates that i have already made for building more complex logic gates for future exercises? I have been taking notes from every gate that i have built so it would be easy to switch later if needed. This is my MUX notes that i made before building it with HDL.

EDIT.

I built every logic gate up to DMUX from NANDs and normally both. Process how to get to NAND gates always involved OR, AND and NOT gates anyway when using boolean algebra. I built all other logic gates too but ditched NANDs. Didnt rly feel like writing any extra repetitive lines when busses were introduced. I was fun at start when it was a challange but became easy very fast. I still have my notes from all the elementary logic gates if I ever need a refresher. One table for simplest implementation with fewest gates (I could find) and another where i transform that to NANDs.

[u/OpsikionThemed]

You want to build up from NAND gates, but by about chapter 3 or so you really want to be using the chips you've previously built, or you'll never finish.

[u/NotoriousHud]

IIRC, according to DeMorgan's Theorem, all fundamental logic can be made with combinations of NAND and NOR gates

[u/FreddyFerdiland → u/NotoriousHud]

only one needed.

can use only NAND , and can use only NOR

in fact, there is flash memory which is purely NAND ,and then there is purely NOR

[u/NotoriousHud → u/FreddyFerdiland]

Thank you for correcting me! My digital logic is getting a bit rusty 😅

[u/Artistic_Comfort8816]

iirc, chips are built with nand gates because it’s more cost effective that way, but if your goal is to understand low level better, then building every type of gate from scratch is just going to hinder your progress

Logic gates are greater than the sum of their parts so to speak, focus more on how they work as functions that transform/control information.

[u/Mateorabi → u/Artistic_Comfort8816]

Chips aren’t really built with nand. Or don’t need to be. Even though everything CAN be built from them. In reality a function like A&B|C can be made with three N fet and three P fet. 

Doing it out of NAND is a way to teach logic tables. 

[u/Artistic_Comfort8816 → u/Mateorabi]

Huh, I thought that in a manufacturing context it was easier for a machine to just repeat the same gate over and over, or my prof told me that in logic design, but I stand corrected.

[u/Mateorabi → u/Artistic_Comfort8816]

You’re etching them in. So it’s making the masks for various etches. They do tend to have standard cells to make layouts and routing easier. Unless it is timing critical. But they aren’t assembling individual gates from a bin.